Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

BAD Block config in NAND Verilog Model !!

Status
Not open for further replies.

vizpal

Member level 2
Joined
Apr 26, 2007
Messages
44
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,519
micron nand verilog model

I have downloaded a NAND Verilog Model from the Micron Site. I want to check if my NAND Controller is performing Block Hunting correctly.

For this how can I create some BAD Blocks.

I understand that I need to create some value other than 8'hFF in the spare region to create a BAD Block .

I want to know how this can be done in the Verilog Model.... :!:

Please help me dude's....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top