sun_ray
Advanced Member level 3
- Joined
- Oct 3, 2011
- Messages
- 772
- Helped
- 5
- Reputation
- 10
- Reaction score
- 5
- Trophy points
- 1,298
- Activity points
- 6,828
Can each of the write data from an AXI master be valid for three clock cycles in a write burst transfer of AWLEN 5? If yes, please write the reason behind an AXI master can keep the data for three clock cycles instead of one clock cycle.
Regards
Regards