Automatic layout in Cadence and relevent post-layout simulations

[electronics20]

Automatic layout in Cadence and relevant post-layout simulations

Hi
I have designed a CMOS Latch with 17 transistors in HSPICE through 0.18um TSMC technology. However, I prefer to utilize cadence for providing a layout. Do I benefit form automatic layout generation in cadence? if so, Is this automatic tool suitable for post-layout simulation as well?
thanks a lot

 

[erikl]

Re: Automatic layout in Cadence and relevant post-layout simulations

... I prefer to utilize cadence for providing a layout. Do I benefit form automatic layout generation in cadence?

Yes, you can, with the Virtuoso XL tool. But don't expect to get a tight - an optimized layout in terms of area consumption. It will just instanciate the correct transistors and their connections, same as you locate them in your schematic - with selectable distances.

Anyway this will allow for considerable time savings in layout creation, but then you have to get such an automatic layout into a reasonable form (re. aspect ratio, tightness, and short connectivity), which also may concern the individual transistors themselves (multiplication, fingering maybe are controllable, depending on the PCells used).

Is this automatic tool suitable for post-layout simulation as well?

This is totally independent of the automatic layout creation. Virtuoso comprises Extract, DRC, LVS and netlisting tools, so you can extract any layout and netlist it for post-layout analysis.