mentor DFT tools have to translate verilog simulation library to DFT libraries.
But when I verify DFT libraries with IcVerify command . It invoke a modelsim .
I currently have ncverlog simulator . if I need to verify DFT libraries translated from verilog simulation libraries with ncverilog ,what i should do ?
If I were you, I'd just inspect your log file generated by the libcomp - and iff there are no problems, just use the library - don't worry about simulating it. I've had decent luck with that approach.
I've used boh Mentor and Synopsys tools in the past.
There was a situation where libComp generated a warning about an unsupported udp construct of some sort. And it caused no problem immediately, because the design did not use that cell - but later on it did, and the ATPG did not work, and it took me awhile to figure it out.
Most standard cell library vendors (TSMC, Artisan, etc.) provide a Mentor library with the library. Make sure you don't have that before using libComp instead.
No, I did not simulate with Modelsim - what I did was trust the results, as long as there were no warnings in the libComp log file. But I was the only user of the FastScan library.
Now if I were developing a library for other's use, I'd find a way to hack the verify script and simulate it.
Seen that before. It's not really an issue, because as you may know , notifiers are for simulation, and flag timing violations and such, which have nothing to do with ATPG.
That said, however, it seems libComp should at least hook those up with tiex primitives, so you don't get the message.