ATPG issue with testbench of STIL format

[leeguoxian]

Dear All :

I run simulation with the verilog testbench outputed from Tetramx , both parallel and serial , and the simulation was good .
Then I tried simulation with testbench of STIL format, and it failed .

Can anyone suggest me how to solve this problem ?


Best wishes
leeguoxian

 

[leeguoxian]

Re: ATPG issue 2

Dear All

I checked the simulation waveform , and found out that there was not any clk during the capture_clk period.
Does anyone experienced the same situation ? I really need your help! Thx!

 

[leeguoxian]

Re: ATPG issue 2

Dear All :

Simulation with file of STIL99 format was good, but it failed with STIL file .
Anyone have any suggestion ?

Best wishes
leeguoxian

 

[dig_des]

Re: ATPG issue 2

Can you check your load_unload procedure and confirm that the capture
clocks are indeed declared there?

 

[leeguoxian]

Re: ATPG issue 2

Dear All :

When I run simulation , I check the waveform and I found the mismatch happened as the follow pic :

From the image, Q isn't become high when the capture clock pulse arrive. Right ?
This happened before, and that is because I didn't use "nospecify" option in VCS simulation. But I did use "nospecify" this time.
Anyone can help we with this problem ?

Thanks

 

[newcpu]

ATPG issue 2

Could you provide part of your log file of verilog pattern simulation? The stil simulation should succeed if verilog pattern is OK.