I run simulation with the verilog testbench outputed from Tetramx , both parallel and serial , and the simulation was good .
Then I tried simulation with testbench of STIL format, and it failed .
I checked the simulation waveform , and found out that there was not any clk during the capture_clk period.
Does anyone experienced the same situation ? I really need your help! Thx!
When I run simulation , I check the waveform and I found the mismatch happened as the follow pic :
From the image, Q isn't become high when the capture clock pulse arrive. Right ?
This happened before, and that is because I didn't use "nospecify" option in VCS simulation. But I did use "nospecify" this time.
Anyone can help we with this problem ?