rameshsuthapalli said:hello
i think u r problem is bcz of the violations present in the design after synthesis.make sure of those violations to be fixed before u run the simulation or plz run the simulations at no_delay mode of the nc verilog.
bye
rameshs
2. by checking your flow, you had scan-chain reordered during PR, so you should regenerate the ATPG pattern using post-layout netlist, and surely the old patterns wont be useful.
jackson_peng said:well, that's all right.
then i suggest you to follow the third recommend to check whether your layout flow might violate the netlist.
jackson_peng said:actually, check_test perform the DFT design rule check, rather than the chain order. and i wonder your PR flow would change the scan order, even thought that sound impossible.
usually, scan-chain is de-stitched and perserved before CTS&Routing, and re-stitched after optimization.
and i've not try other flows, so its beyond my experience to figure out where might be the problem.
regards.
rameshsuthapalli said:Hi leeguoxian,
u r flow is correct upto 7 .
8 step is wrong step.bcz we must use the MAX or min delay mode with the SDF annotations. since the simulator will assume in such a way that each cell will contribute an unit delay and it will analize the path so that there may be a chance of getting the setup and hold problems in the postlay so i recomende to use atpg simulations in the postlayout must be done in both min and max delay mode of the simulator with the proper sdf file.
regards
rameshs
rameshsuthapalli said:Hi leeguoxian,
i will explain u. in the post layout the if u run in the no delay mode.these r the problems compared to the prelayout simulations.
1)take this case there is a path directly going from q pin to next flop d pin with a simple and gate. in the prelayout stage there is no buffers(clock tree) in the clock path. so there is no hold violation.
2) in the abouve case take it in postlay stage the tool inserted two more buffs in the clock path compared compared to prelayout .
it will think that the capture flop is under hold problem. so the atpg simulations will failed.
regards
rameshs
rameshsuthapalli said:Hi leeguoxian,
the vcs simulator will consider the unit delta delay for all the cells for caluculationg the simulation results.
u can see that while running the simulator it is saying that 0.5 or 1 is conistantly assigned as delay for each cell. the no delaymode will not give any problem for setup but it will give problem for hold in postlay simulations.
plz run the STA with out the false paths and multy cycle paths.
so u will get the violation as some x with the clock time period ad Y.
then run the simulations with the period of the scan clock as "X+Y".
that means u must re genetarate the tpg vectors with scan clock havins X+Y period.
if problem is still there then see wether there is any hold violations in the above sta reports.
regards
rameshs
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