ATPG and pattern Simulation mismatch (Debug pattern 1/0 and 0/X) ?

[vbharath]

Hi
1.) Can any give source for simulation mismatch, if possible explain with one example?
2.)Why do we do no timing simulation, what would be the reason for doing no timing simulation what errors we may get in no timing simulation and how to debug?
3.)why latches are made transparent during scan?


Regards,
Bk

 

[dpaul]

While generic answers to the questions posted you can find through a search engine, w.r.t. ATPG pattern simu mismatch, there is already an existing discussion on EDABoard.

https://www.edaboard.com/threads/343302/

 

[slutarius]

For question number 2, the most practical reason is about running time when we attached the annotation delay into simulation. Especially, it is painful for slow clock scan test.