ATA controller design in FPGA

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vhdl pata interface

Now i have an important problem, which is how to design complex digital system
using Verilog HDL. If u have some referenece , please send to me :
mynamezyq(at)163.com

Thank u very much!!!
 

ide ata lba high low data sector mid

Cable 40 or Cable 80 is not the matter.

The value "0xff7f" is read to indicate the following two things:
1. You can't assign the correct register value. When you write, please make sure the bus is controlled by the host.
2. When you read, you must make sure you read from the bus controlled by the device.

I just wrote the some code about the ATA-7 and I can read the register value easily.

Suggest that you can use the IDE analysor to check your protocol.
 

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