Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ATA controller design in FPGA

Not open for further replies.


Junior Member level 3
Feb 22, 2006
Reaction score
Trophy points
Activity points
fpga ata

when design ATA host , i met with the problem:after hardware reset, power on or software reset, the host designed by me , has red the value from the registers such as status register, LBA low register , LBA High register LBA mid register, or Device register in ATA hard disk(MAXTOR 250G). To my surprise, the values are the same: 0xFF7F. Why????????? help me , thank u again !!!!

hdd fpga

Could be your cable is broken
fpga hard disk

the cable is ok, no problem.
The time sequence is designed according to ATA/ATAPI-6. However, the host cannot read the register block.After hardware reset, DD[15:0] == FF7Fh.
But all the values read by the host are FF7Fh. Why? :cry:

sata controller vhdl

just recheck for proper power up sequence. and PoR values of those registers.

ata host controller in fpga

check the hard disk configuration.
i think u have configured(using those jumpers) the harddisk as slave.
reconfigure it as master.

fpga hard disk controller

Whatever the ATA harddisk(MAXTOR 250GB PATA 133 HDD) is configured(using the jumper) as master or slave mode, the results are the same: REGISTER BLOCK
can't be written or read.

Only J50 is usually OK.
master mode:
o o — o o
o o o o o
J50 J48 J46 J44 J42

I don't know why.......
Help me, thank u from my heart!!!

ata atapi fpga

which pio mode are u using to read the hard disk registers?

hard disk controller design

Who have made ATA HDD host controller to read and write data from/to ata hard disk ?
mode :pIO, Ultra DMA133 or Ultra DMA100 .
I have seen IDE core on opencores, it is almost only time sequence coordination.
but how to design a host controller with FPGA like CPU to transfer to/from ATA devices? I have written FSM in Verilog HDL, but when i test it, found that the registers block can't be operated:the values can't be read or written from registers in HDD.

the master operates at register/PIO mode0,the values red by host are 0xFF7F.

problems with read or write register fpga

Who have done the ATA HDD(hard disk)controller ? Please help me, 3x

pio hard disk sector count register

0 ,i know that Pin DD7 is connected with pull-down ristance.So it is always "0".
But how to read/write register block correctly?

ata fpga

3x, now i will do UDMA MODE TRANSFER.
help me, 3k u !!!!


cheak that you have made the hard disk driver the main or slave,and everytime you write the read command cheak if you have indicated the hard disk driver properly!

Added after 5 minutes:

Also you can do the work below:First,you can cheak if the address you write are correctly,second,you can cheak if you have reset the hard disk driver properly and initiate it with right parameters!

fpga ata disk

Now I have a fact that is HDD operates on default PIO mode after HDD reset. The host can write/read data:512B to/from a sector in HDD.
TO set device PIO mode 4, the host writes 8'h03 into the feature register, 8'h0C into the sector count register, and commond code:8'hEF into the command register.
However, read/ write time cycle don't reduce.
Why? Help me, please

hdd fpga read write

Now I am testing my program that supports PIO mode 0...4,but when continully
read/write data from/to the cache of Maxtor HDD,it goes wrong more with the more sectors operarted successively.

hdd fpga

please send me too...


fpga harddisk

When I design HDD host controller with Ultra DMA Mode 5(ie. UDMA100),
after 256 words writtten, the value is 51h in the status register.
I infer that CRC data is error,so how to solve the problem?
help me,please.
3x u

ata fpga

make sure u r using 80 conductor cable

sata disk controller fpga

Do you have any timing problem with the FPGA ?
Also are u sure that the device is well working or u don't have info about it.


ata 7 fpga

I am sure that i using 80 conductor cable , 256 words written, and INTRQ asserted
then the value is 51h of the status register,ICRC asserted(1) in the Error register.
In addition, CRC rules come from ATA/ATAPI 6.
Help me,please
3k u

ata controller in fpga

do u get the crc error in lower speed udma mode also?
if crc error are seen only in mode5 then there could be some signal integrity issues in the board. make sure the signals are properly terminated.
Not open for further replies.

Part and Inventory Search

Welcome to