asynchronous level-shifter design

[kaka.alonso]

what is the mechanism of asynchronous level-shifter?
it is said a contention exists between the pull-down devices and the feed-back path
how to understand it?
thx

 

[apallix]

Following is an explanation of the circuit behavior. I hope it is not too confusing.

first some naming:

pu_l : left pull-up pfet
pu_r: right pull-up pfet

pd_l: left pull-down nfet
pd_r: right pull-down nfet

int_l: drain of pd_l and drain of pu_l
int_r: drain of pd_r and pu_r

initial condition:
D=0, Db=1
int_l=1, int_r=0
Q=0, Qb=1

So, initially pd_l is turned-off and pu_l is turned-on and this pfet holds int_l at '1'. pd_r is turned-on and holds int_r at '0' while 'pu_r' is turned off.

Circuit behavior when there is a rising transition from 0->1 at input 'D':

When input 'D' rises and 'Db' falls, pd_l turn-on and pd_r turns-off. At that time, pu_l is still turned-on. This is the contention that you were asking about... pd_l and pu_l both turned-on at the same time. The nfet pull-down devices in the asynchronous levelshifter are sized to be much stronger than the pull-up pfets. So, when pd_l is turned-on it is able to fight pu_l and pull-down int_l from 'VDD_high' to much less than 'VDD_high - Vthp' where Vthp is the threshold voltage of the pfets. This will turn-on pu_r and this pfet will start charging int_r from 0 to VDD_high. This will turn-off pu_l and pd_l is able to pull-down int_l all the way to '0'.

The circuit behavior is the exact opposite when there is a falling transition at 'D'