abhinavpr
Junior Member level 2
Hi ,
is using Flip flops as FIFO memory in an ASYNCHRONOUS FIFO a standard practice in the industry?. For smaller fifo sizes like 8-16 depths fifo inferred memory should be used.
but flop inferred memory will have non registered output and that would result in getting the read data in the same cycle in which rd_en is placed.
what would the solution be?
register the output data by adding additional flop stage or change the controlling logic?
-abhinavpr
is using Flip flops as FIFO memory in an ASYNCHRONOUS FIFO a standard practice in the industry?. For smaller fifo sizes like 8-16 depths fifo inferred memory should be used.
but flop inferred memory will have non registered output and that would result in getting the read data in the same cycle in which rd_en is placed.
what would the solution be?
register the output data by adding additional flop stage or change the controlling logic?
-abhinavpr