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asynchronous FIFO design

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KUMARGAURAV

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Hi, can anyone help me with the synthesizable verilog code for Asynchronous FIFO?
regards
 

KUMARGAURAV

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Hi thanks, but could you please explain the synchronizers implemented and the address logic.


Code dot - [expand]
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//'EqualAddresses' logic:
      assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
  
      //'Quadrant selectors' logic:
    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &                           (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
                              
      assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &                          (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
                           
       //'Status' latch logic:
      always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
          if (Rst_Status | Clear_in)
              Status = 0;  //Going 'Empty'.
          else if (Set_Status)
              Status = 1;  //Going 'Full'.
              
      //'Full_out' logic for the writing port:
      assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
      
      always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
          if (PresetFull)
             Full_out <= 1;
           else
             Full_out <= 0;
            
     //'Empty_out' logic for the reading port:
    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
    
      always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
          if (PresetEmpty)
            Empty_out <= 1;
          else
            Empty_out <= 0;



If possible can anyone please explain the block of code written above?
thanks and regards
 
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sharath666

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U are comparing the read and write pointers to determine when the FIFO goes full and empty. Use numerical values for all signals used above. U will understand better. Imagine a depth of say 16 which gives ADDRESS_WIDTH as log(16) (== 4).
 
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KUMARGAURAV

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Hi, can anyone help me with the synthesizable verilog code for Asynchronous FIFO?
regards

A simple search engine query would have found what you are looking for.

https://lmgtfy.com/?q=asynchronous+fifo

The second link at asic-world has code.

Hi Sir, I already have gone through the code given in the second link but I am not able to understand the quadrant selectors logic, status latch logic, full out logic and empty out logic and how synchronizers and comparators are implemented. It will be greatly helpful to me if you elaborate those implementations.
Thanks in advance
 

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I'm not really interested in analyzing the asic-world code. Usually code found on tutorial websites is not the best quality code around. I figured, since you came asking for code I'd point out that you can find code of dubious origin and quality by doing a web search.

But the real question wasn't "I want some code for an asynchronous FIFO" but was actually supposed to be "I want to understand how to implement an asynchronous FIFO".


Try looking at the paper by Cummings...https://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf and the interesting analysis of the original asynchronous FIFO design if you are so inclined to really understand FIFO design...https://www.coolverification.com/2006/12/a_colleague_why.html
 
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