Asynchronous FIFO design for the video controller

100mhz fifo

Hello,

i have the following FIFO:

width = 24 bits (3 bytes)
Depth = 2048

I will use it to transmit pixel color data from 1024x768x24Bpp display.
Total amount of memory such picture occupies is:
1024 x 768 x (3 bytes) = 2 359 296 bytes

So i will need to transfer 2 359 296 bytes of data.
Transfer rate: 100 MHz
Receive rate: 65 MHz

If to follow to the formula, which i see in Google regarding FIFO depth calculation:

Depth = W - ( (W * P * Fr) / (Fw * N) )
W = total amount of bytes to send [2 359 296]
N = number of bytes transmitter sends per transmit clock [24 bits,or3 bytes]
P = number of bytes receiver receives per receive clock [24 bits,or3 bytes]
Fw = transmitr frequency [100 MHz]
Fr = receive frequency [65 Mhz]

So, Depth = 2 359 296 - ( (2 359 296 * 3 * 65*10^-6) / (100*10^-6 * 3) ) =
= 825 753 bytes...

My FIFO is 3 bytes width, and 2048 bytes depth... total of 2048 x 3 = 6 144 bytes...

does this mean that My FIFO depth is not enough for such operation??

or maybe i have some error in calculation?

cuz its hard to beleive for me that i need such a big FIFO...

thanks in advance!

calculate video fifo depth

fifo depth will depend on how frequent you read
if you read every alternate clocks then a fifo depth of 256 should be sufficient for you.
check this link to know more about fifo depth calculation
https://www.asic-world.com/tidbits/fifo_depth.html