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asynchronous fifo design flag generations

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shaiko

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I'm designing an asynchronous FIFO.
While the rightmost bits of the write and read pointer vectors are used for the actual write and read addresses - the MSB is used only to set the control flags (almost full \ full \ almost empty \ empty).
The signals are defined as follows:
Code:
signal wp , rp_from_read_clock_domain : unsigned ( x downto 0 ) ; -- read and write pointers
signal write_address , read_address : unsigned ( x - 1 downto 0 ) ; -- read and write addresses
Here's the write clock domain process where I set the "almost full" and "full" flags (I use a similar process in the read clock domain to set the "almost empty" and "empty" flags).
Note: you won't see it in my code - but consider the pointers to be gray enconded, synchronized to the other clock domain and decoded back to binary for use. with this in mind, please tell me what you think about the write domain process:
Code:
write_address <= wp ( wp ' high - 1 downto 0 ) ;

process ( write_clock , reset ) is
begin
	if reset = '1' then  
		afull <= '0' ;
		full <= '0' ;	
		wp <= ( others => '0' ) ;
	elsif rising_edge ( write_clock ) then  
		almost_full <= '0' ; 
		full <= '0' ;  	
		if write_request = '1' then
			wp <= wp + 1 ;
		end if ;
		if 
		wp ( wp ' high - 1 downto 0 ) = rp_from_read_clock_domain ( rp_from_read_clock_domain ' high - 1 downto 0 ) and 
		wp ( wp ' high ) /= wp ( wp ' high ) then
			full <= '1' ;
		else
			full <= '0' ;
		end if ;	
		if rp_from_read_clock_domain ( rp_from_read_clock_domain ' high - 1 downto 0 ) - wp ( wp ' high - 1 downto 0 ) <= afull_threshold then
			afull <= '1' ;
		else
			afull <= '0' ;
		end if ;	
	end if ; 	
end process ;
 

permute

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"wp ( wp ' high ) /= wp ( wp ' high )"
"x /= x"
"false"

you will never assert full.
 
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    shaiko

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shaiko

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Sorry,
This is what I meant:
Code:
write_address <= wp ( wp ' high - 1 downto 0 ) ;

process ( write_clock , reset ) is
begin
	if reset = '1' then  
		afull <= '0' ;
		full <= '0' ;	
		wp <= ( others => '0' ) ;
	elsif rising_edge ( write_clock ) then  
		almost_full <= '0' ; 
		full <= '0' ;  	
		if write_request = '1' then
			wp <= wp + 1 ;
		end if ;
		if 
		wp ( wp ' high - 1 downto 0 ) = rp_from_read_clock_domain ( rp_from_read_clock_domain ' high - 1 downto 0 ) and 
		wp ( wp ' high ) /= rp_from_read_clock_domain ( rp_from_read_clock_domain ' high ) then
			full <= '1' ;
		else
			full <= '0' ;
		end if ;	
		if rp_from_read_clock_domain ( rp_from_read_clock_domain ' high - 1 downto 0 ) - wp ( wp ' high - 1 downto 0 ) <= afull_threshold then
			afull <= '1' ;
		else
			afull <= '0' ;
		end if ;	
	end if ; 	
end process ;
 

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