asynchronous bus multiplexer in verilog: always+wire

[buenos]

hi

i always worked in VHDL, and I did my combinatorial assigments in processes with nicely readable if/elsif/else statements.
I was trying to do the same in verilog in an always block, but the synthesiser gives an error. it seems the output signals have to be registers and driven by a clock. this is actually a problem, because i want my multiplexer to propagate the input signals to the output without one clock cycle delay.
i could use this:
assign out= (dsdfsdf)? in1 : (fdghgyugh)? in2 : (nuuitjk)? in3 : in4
but because of the long signal names, it wouyld not be human readable, so i dont like it.

how can i write something similar to the vhdl async-process with if statements in verilog?

 

[dcreddy1980]

assign out= (dsdfsdf)? in1 : (fdghgyugh)? in2 : (nuuitjk)? in3 : in4 

equivent in always block :

always@*
begin

if(dsdfsdf)
   out = in1;
else
   if(fdghgyugh)
      out = in2;
   else
      if(nuuitjk)
         out = in3;
      else
         out = in4;

end

 

[tkbits]

The left hand side of an assignment within an always must be "specified" as reg. Whether it is registered or not depends on whether the sensitivity list has signals listed as posedge/negedge or not.

// synchronous
reg q;

always @(posedge clk)
begin
  q <= d;
end

// asynchronous
reg output1;

always @(input1 or input2)
begin
  output1 = input1 & input2;
end

 

[buenos]

what is the point in "reg" if it is asynclronous? will it relly be a d-flip-flop?

actually i found what i was looking for, i think: use an assign statement with putting the different cases into different lines:

assign out=
//if dfgdfg
(dfgdfg)?
  1:
//elsif dfgdfgdfg
(dfgdfgdfg)?
  1:
//elsif dfgdfg
(dfgdfg)?
  0 :
//else
  1;