buenos
Advanced Member level 3
- Joined
- Oct 24, 2005
- Messages
- 960
- Helped
- 40
- Reputation
- 82
- Reaction score
- 24
- Trophy points
- 1,298
- Location
- Florida, USA
- Activity points
- 9,116
hi
i always worked in VHDL, and I did my combinatorial assigments in processes with nicely readable if/elsif/else statements.
I was trying to do the same in verilog in an always block, but the synthesiser gives an error. it seems the output signals have to be registers and driven by a clock. this is actually a problem, because i want my multiplexer to propagate the input signals to the output without one clock cycle delay.
i could use this:
assign out= (dsdfsdf)? in1 : (fdghgyugh)? in2 : (nuuitjk)? in3 : in4
but because of the long signal names, it wouyld not be human readable, so i dont like it.
how can i write something similar to the vhdl async-process with if statements in verilog?
i always worked in VHDL, and I did my combinatorial assigments in processes with nicely readable if/elsif/else statements.
I was trying to do the same in verilog in an always block, but the synthesiser gives an error. it seems the output signals have to be registers and driven by a clock. this is actually a problem, because i want my multiplexer to propagate the input signals to the output without one clock cycle delay.
i could use this:
assign out= (dsdfsdf)? in1 : (fdghgyugh)? in2 : (nuuitjk)? in3 : in4
but because of the long signal names, it wouyld not be human readable, so i dont like it.
how can i write something similar to the vhdl async-process with if statements in verilog?