ASSURA extraction Problem

[iamvictor]

I am using ASSURA within IBM cms9flp design kits.

1. There is no problem with DRC and LVS, but the extracted view generated by DRC only have all the pins in the view, and no component at all!
If it passed the LVS, I believe the extraction should be correct. So is this the display problem or something else?

2. If I use RCX I can get the extracted view. All parastic R & C are shown with reasonable values, but the parameters with components didn't correspond to the layout parameters.
For example: if I check the extracted transistor symbol porperty, the W was always the minimum size no matter how I double it in the layout. The same for VNCAP, I use M1-M6 in the layout, but if I check the cap symbol porperty in the extracted view, it was M1-M1.
I guess, all the extracted components were all with parameters of stardard cell (minimum size). Also, the "view name" in the "porperty tab" of these components are "symbol" instead of being "auLVS" or "vipcell". If should not be like this.
Could anyone give me a clue?

Many thanks!

Victor

 

[iamvictor]

Can someone help me. It is really urgent, the chip tapeout deadline is coming. Thanks.

 

[Loktik_Vitalij]

Describe consecutively your actions.
the steps of the extraction

 

[Teddy]

I guess you shoul dlook into the extraction command file.
Then I suppose there will be a switch for RCX and there just verify the symbol / auLVS views.

Another solution is to ask IBM - if you are good customer they will respond quickly.

 

[bitcat]

maybe problem with its PDK,
if you use different version of tools or under different enviroment,skill will not work very well.
an private method,use PDK build by youself,or use res cell by youself.thus ,extract cell will use your cell ...

 

[luckypearl25]

the problem could also be that,you are trying to overwrite some previously extracted file.
Delete av_extracted file or give a different name to the extracted file and try it out.

 

[shahriar22nd]

Hi iamvictor,
I am using Assura with cms9flp like you. You mentioned that, you had no problem with DRC and LVS. I passed DRC flawless, but having problem in LVS with Assura. Help docs of the PDK states that, Assura needs two files exclusively- IBM_PDK/cms9flp/V1.2.0.0/cdslib/cms9flp/subcircuit.cdl.assura and IBM_PDK/cms9flp/V1.2.0.0/utils/assura_cdl_processor.pl, but I see, none of them are present in the PDK.
Would you please tell me how can I proceed for Assura LVS without these files?
Thank you,