assining value to register

[rockgird]

hii ,
m faicin a prob, while assing value to "reg" - port.

actually this is part of my code

module fulladd1(s, co, a, b, ci);
output co, s;
wire co, s;
input a, b, ci;
wire a, b, ci;
wire a_b_o,b_ci_o,a_ci_o;
xor a_b_xor( a_b_o, a, b);
xor s_c_xor( s, a_b_o, ci);
and a_and_ci( a_ci_o, a, b );
and b_and_ci( b_ci_o, a_b_o, ci );
or co_or( co, a_ci_o, b_ci_o );
endmodule

this works

but when i use this

module fulladd1(s, co, a, b, ci);
output co, s;
reg co, s;
input a, b, ci;
wire a, b, ci;
wire a_b_o,b_ci_o,a_ci_o;
xor a_b_xor( a_b_o, a, b);
xor s_c_xor( s, a_b_o, ci);
and a_and_ci( a_ci_o, a, b );
and b_and_ci( b_ci_o, a_b_o, ci );
or co_or( co, a_ci_o, b_ci_o );
endmodule

it dosen't work !!

plz help me out.

PS:- m usin Active HDL 6.3 for writin verilog prog.

thanx in anticipation

 

[freeinthewind]

u must assign a value to register by an clock.

 

[benzwishc]

u use the intantiated primitive modules to assign the output, but actually it just equals to have continuous assignment in this progress, also it have to be the wire type, if you want to have reg type, u have to have a process, just always block, you can resort something else about this topic to verilog tutorial