library ieee;
use ieee.std_logic_1164.all;
----------------------------------------
entity Mux_21 is
generic
(
WIDTH : integer := 8
);
port
(
FirstInput : in std_logic_vector(WIDTH-1 downto 0);
SecondInput : in std_logic_vector(WIDTH-1 downto 0);
Sel : in std_logic_vector(0 downto 0);
Output : out std_logic_vector(WIDTH-1 downto 0)
);
end entity; -- Mux_21
----------------------------------------
architecture Arch of Mux_21 is
begin
Output <= FirstInput when Sel = '0' else
SecondInput;
end architecture; -- Arch