[SOLVED] assigning std_logic to std_logic_vector

[anonymous.]

I always use generics in my designs, for example I use WIDTH parameter with registers to specify how many bits it can hold, This has one problem though, If I need to use WIDTH=1 (a single Flip Flop) Design Compiler complains about signal assignment (Assigning std_logic from the top design to std_logic_vector from the register), Because this issue could happen at any stage of the design I decided to always replace all std_logics with std_logic_vector(0 downto 0) and that was it. Design Compiler never complains again about these.

Modelsim however does not accept this, this simple Mux example:

library ieee;
use ieee.std_logic_1164.all;
----------------------------------------
entity Mux_21 is
	generic
	(
		WIDTH 				: integer 	:= 8
	);
	port
	(
		FirstInput			: in 		std_logic_vector(WIDTH-1 downto 0);
		SecondInput			: in 		std_logic_vector(WIDTH-1 downto 0);
		Sel 				: in 		std_logic_vector(0 downto 0);
		Output 				: out 		std_logic_vector(WIDTH-1 downto 0)
	);
end entity; -- Mux_21
----------------------------------------
architecture Arch of Mux_21 is
begin

	Output 		<= FirstInput 		when Sel = '0' else
			   SecondInput;

end architecture; -- Arch

generates this error :

No Feasible entries for infix operator "="

How to solve this issue in a manner that does not generate errors in both Design Compiler and Modelsim?

 

[FvM]

How to solve this issue in a manner that does not generate errors in both Design Compiler and Modelsim?

By observing VHDL syntax rules

when Sel = "0" 
respectively
when Sel(0) = '0'

It's not obvious at first sight why sel should be std_logic_vector, but of course it can.

 

[anonymous.]

That was easier than I thought, Thanks a lot.

 

[anonymous.]

Sorry to use the same thread again, But if I haven't used std_logic_vector(0 downto 0) what would have been the solution?? how to assign std_logic to std_logic_vector(0 downto 0) ?

In more details again, I mean in some cases I have to use designs with generics set to only 1, resulting in a signal of type std_logic_vector(0 downto 0). In the top designs these signals are assigned to std_logic signals which generates a type mismatch

[Error] Mismatch between type IEEE.STD_LOGIC_1164.STD_LOGIC_VECTOR of formal port INPUT and type IEEE.STD_LOGIC_1164.STD_ULOGIC of actual

 

[rca]

in the instantiation, you could unroll the vector:
toto(
a(0) <= a;
a(1) <= b
);

but the "best" solution is never used std_logic, and only std_logic_vector(0 downto 0).