Assigning clock pin in XSA 50

[magnetra]

I'm using XSA 50 board. I have successfully implemented combinational circuits in it. But I'm having problems implementing sequential ckts which require clock. I'm using Web Pack from Xilinx, and it provides a tool PACE for pin assignment. The master clock pin for XSA 50 is P88, but when I assign P88 to my "CLOCK" port of VHDL entity, it doesn't accept. Where could I be going wrong?? Any idea?

Reagrds
M

 

[bis_]

Check if there are no other signals/pads previously assigned to that pin. Check if the FPGA defined in the project is exactly the same as in board schematics.

 

[bubu321]

hi,

- look at this

**broken link removed**

σ

 

[tkbits]

Make sure your CLOCK is an IN port. P88 will not support INOUT or OUT.

Have you already connected an IBUF to the CLOCK signal? If so, that is incorrect for P88. P88 is connected to an IBUFG, which can output only to a BUFG or a CLKDLL. You can explicitly connect the IBUFG and BUFG components, or else let XST (Webpack) "create" and connect them automatically.

 

[yego]

Check if your clock input pin is of the same voltage standard as all other pins of this bank.
All pins in a given bank must be of the same I/O standard.

regards, yego.

 

[magnetra]

I tested pin 88 of XSA 50 board with an oscilloscope and got a stable 100MHz sine wave.
But I need rectangular pulse clock? what do I do? Are there any other pins designated for purpose of clock?

Added after 5 minutes:

Does any have information on Electrical Characteristic of XSA board?