assigning a long array to a short array

[shaiko]

type long_array is array ( 0 to 3 ) of unsigned ( 8 downto 0 ) ;		
type short_array is array ( 0 to 3 ) of unsigned ( 7 downto 0 ) ;	

signal x : long_array ;
signal y : short_array ;

I want the lower 8 bits of each cell of array x to be assigned to the matching cells of array y.
I.E copy array x into array y while discarding the MSBs of array x.
This is what I wrote:

y <= x ( ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ) ;

Modelsim compilation fails with the following message:

Slice range direction (downto) does not match slice prefix direction (to).

What's the reason?
From what I see, the slices range direction matches well...

 

[K-J]

What's the reason?
From what I see, the slices range direction matches well...

y <= x ( ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ) ;

It looks like you have too many parentheses. I think the following is what you want, but I haven't tested it

y <= x  ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 );

Kevin Jennings

 

[shaiko]

tried this:

y <= x ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ;

The newer error says:

Cannot resolve slice name as type short_array.

 

[K-J]

tried this:

y <= x ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ;

The newer error says:

That's because you defined both 'long_array' and 'short_array' as types instead of subtypes so you will need a type conversion function to convert from one to the other. So your choices are:
- Create a function that takes as input a 'long_array' and returns a 'short array' and keep the type definitions that you have
- Create a more general type, then make 'long_array' and 'short_array' be subtypes of the more general type. That way you don't need any type conversion function.

Example:

type array2d is array ( natural range <> ) of unsigned; -- Will need to compile with VHDL-2008 
subtype long_array is array2d( 0 to 3 ) ( 8 downto 0 );
subtype short_array is array2d( 0 to 3 ) ( 7 downto 0 );

Again, not tested.

Kevin Jennings

 

[shaiko]

Well,
Actually my code is much more general then what I wrote at first. This is how it looks now:

type type_array_unsigned is array ( natural range <> ) of unsigned ; -- defined in an external package.

An input port that uses the above custom type is defined as follows:

x : type_array_unsigned ( 0 to a - 1 ) ( b downto 0 ) ; -- a and b are entity generics.

A subtype and a corresponding signal are defined as follows:

subtype short_array_unsigned is type_array_unsigned ( 0 to a - 1 ) ( b - 1 downto 0 ) ;
signal y : short_array_unsigned ;

The rightmost bits of array input port x are assigned into array y :

y <= x ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ;

Compilation fails with the following message:

(vcom-1012) Slice range direction (downto) does not match slice prefix direction (to).

 

[K-J]

genx : for i in x'range generate
    y(i) <= x(i)(x(0)'high - 1 downto 0);
end generate genx;

 

[shaiko]

This works well.
Any idea as to why it fails in the prior examples? Can you point any VHDL rule violations?

 

[TrickyDicky]

You can only slice into a single dimension. Previously, you had two slices:

y <= x ( x ' range ) ( x ( 0 ) ' high - 1 downto 0 ) ;

where you slice into the first array and 2nd array at the same time. That is not allowed.