asserting valid signals

[anusha vasanta]

Hi all,
is this a proper way of asserting and deasserting my valid signal.

  for (i=0;i< No_Patterns;i=i+1) begin      //apply inputs
  @ (posedge clk)
  #Clk2Q
  data_valid_in = 1;                       //assert valid signals
  cipherkey_valid_in = 1;
  plain_text = data_input_vectors[i];
  cipher_key = cipherkey_input_vectors[i];
  end
  
  @(posedge clk)
  data_valid_in = 0;                      //deassert valid signals
  cipherkey_valid_in = 0;

 

[sharath666]

Yes. It is. The only thing you should remember while asserting valid signals is that these signals should be in sync with the data i.e. the valid should be asserted when the data is corrected and should be brought down otherwise.

 

[anusha vasanta]

thankyou. but here both are asserted and deasserted during posedge of clk how the actual process is gng on internally.

 

[sharath666]

Simulate and observe the waveform and relate it to the code. You will then understand it then...