I have written simple assertion in SV... Can anyone tell me how to execute the same in Questa...? In the sense exact command or steps to be followed to exexcute it...?
I have written simple assertion in SV... Can anyone tell me how to execute the same in Questa...? In the sense exact command or steps to be followed to exexcute it...?
Thank u Very much blooz....
But i want to know the significance of the command- atv log -enable /top..
Because even if i am excluding this i am getting assertion error message if i am intentionally inserting an error to my code....
When complex assertions are triggered, it can be challenging to determine the cause of the failure . Assertions can be logged to the Wave window where activation, success, and failure states are easily identified. Since assertions can have multiple threads in concurrent evaluation,Questasim includes an innovative Assertion Thread Viewer, which graphically shows the complete evaluation of an activated assertion.
---------- Post added at 10:44 ---------- Previous post was at 10:42 ----------
Thank u Very much blooz....
But i want to know the significance of the command- atv log -enable /top..
Because even if i am excluding this i am getting assertion error message if i am intentionally inserting an error to my code....
Try atv log -enable /top_module_name ,just replace the top_module_name with your design's Module name ,do not replace with file name ,just the module name .
I think you did n't use the
Use the +acc=a argument with the vopt command
or -voptargs=+acc=a argument with
the vsim command
atv log
This command enables or disables assertion thread viewing (ATV) for the specified assertion.
Multiple assertions may be specified by their pathnames.
Prerequisites Use the +acc=a argument with the vopt command or -voptargs=+acc=a argument with
the vsim command
•Use the -assertdebug argument with the vsim command