Junior Member level 1
In the question below, the ASM chart shows that value of q_next is compared to 0 to proceed to next state but before q_next is compared, the value of q is already updated with q_next, so if we compare the value of q with 0, will the results be same in terms of timing and other parameters? Also what should be the types of q_next and q? Should they be reg or wire? I have attached the screenshots of the ASM chart and the Verilog code. I also don't understand the timing implications of conditional box, like when in the wait1 state, we check the value of sw and if true, we decrement the counter and then check if counter has reached to zero and then asser db_tick. I want to understand the time flow when we move from wait1 and increment counter and assert db_tick. Are there any clock cycles involved between these stages, that is moving from a state to a conditional box? Also in the verilog code, we use q_load and q_tick to control the counter. Why these signals are used when we can simply control the counter in the states? Is it done to make sure that the FSM (control path) controls the counter (data path)? Please explain. Thanks in advance.