The following is about the ASIC design flow:
Design Specification-->Design Partition-->Design Entry:Verilog Behavioral Modeling-->Simulation/
Functional Verification-->Design Integration and Verification-->Presynchesis Sign-Off-->Synthesize and Map Gate-Level Netlist-->Postsynthesis Design Validation-->Postsynthesis Timming Verification-->
Test Generation and Fault Simulation-->Cell Placement,Scan Chain and Clock Tree Insertion, Cell
Routing-->Verify Physical and Electrical Design Rules
-->Extract Parasitics-->Postsynthesis Timming Verification-->Design Sign-Off-->Production-Ready Mask