ASK Demodulator RFID Tag

[shaikss]

Hi,

I am designing an ASK demodulator for RFID Tags. I have attached the circuit diagram. This is the ckt from IEEE paper.
If you look at the ckt, the first stage is the inverter kind of thing. I didn't get why second NMOS is used for Stage I. Similarly, the second stage is also inverter with two NMOS. Again, the question is why second NMOS. But when I checked the output of that stage, it is acting like a latch. The last stage is buffer.

I generated ASK modulated signal and fed as input to the demodulator. I expected that whenever modulated signal is present, demod output is '1' and when no signal is present, it is '0'. To my great surprise, it is always '1'. I tried to give the input by delaying it. So, for the very first time, because of the delay, I could see a logic '0`' at the output. After the delay, there is signal and so the output is logic '1'. Afterwards, though there is no signal, I don't see logic 0 at the output. Its always high. I assumed that the second NMOS at second stage is acting like a latch. Please let me know how can I redesign it? Or Is my understanding wrong? I have attached the simulated results.

 

[erikl]

(1) MM2 and MM3 behave like one longer transistor: for equal widths you can add their lengths.
(2) The lower NMOS is in off state, just leads leakage current. Don't know if this is correct.
(3) The connection between the output of the 1^st inverter to the input of the 2^nd inverter is missing. If (3) should operate as a latch, an additional connection between the output of the 2^nd inverter to the input of the 1^st inverter is necessary.

 

[shaikss]

(1) MM2 and MM3 behave like one longer transistor: for equal widths you can add their lengths.
(2) The lower NMOS is in off state, just leads leakage current. Don't know if this is correct.
(3) The connection between the output of the 1^st inverter to the input of the 2^nd inverter is missing. If (3) should operate as a latch, an additional connection between the output of the 2^nd inverter to the input of the 1^st inverter is necessary.

Part '3'....I have connected the drains to the gates. I believe the connection is missing in the figure. Yaa, what u said about the operation of ckt is right. But I don't understand whenever signal is there, output should be logic '1' and when no signal present, logic '0' should be at output. I don't see such behavior here. Once the ckt provides logic '1', the output stays on logic '1' though there is no signal at the input. What should be the work around on this ckt, if I want to see my expected output?

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Hi,

I am designing an ASK demodulator for RFID Tags. I have attached the circuit diagram. This is the ckt from IEEE paper.
If you look at the ckt, the first stage is the inverter kind of thing. I didn't get why second NMOS is used for Stage I. Similarly, the second stage is also inverter with two NMOS. Again, the question is why second NMOS. But when I checked the output of that stage, it is acting like a latch. The last stage is buffer.

I generated ASK modulated signal and fed as input to the demodulator. I expected that whenever modulated signal is present, demod output is '1' and when no signal is present, it is '0'. To my great surprise, it is always '1'. I tried to give the input by delaying it. So, for the very first time, because of the delay, I could see a logic '0`' at the output. After the delay, there is signal and so the output is logic '1'. Afterwards, though there is no signal, I don't see logic 0 at the output. Its always high. I assumed that the second NMOS at second stage is acting like a latch. Please let me know how can I redesign it? Or Is my understanding wrong? I have attached the simulated results.

I have uploaded the circuit I have simulated and its results. I have used M2 and M11 to generate ASK modulated signal. The other part is the demodulator circuit which I have uploaded as the first post. Coming to the results, Simulation.png shows the voltage on the nets - "in", "mm_out", "sig_out" and "output". In this plot, I expected that whenever "mm_out" is high, "sig_out" should be low. But this behaviour is never happening. The final plot is Vgs and Vth of M7, M3 and M12.

 

[erikl]

... I expected that whenever "mm_out" is high, "sig_out" should be low. But this behaviour is never happening.

Right. But you can see that the inversion from mm_out to sig_out isn't working correctly.

Above I already suspected (2) that this stage (now: M7-M3,M10) isn't configured correctly, because M10 is off and cannot lead current. Try and change the connection from its gate to its drain (instead of to its source) - or even totally remove M10 (or bridge from M3's source to gnd - just for a trial).

If the latch function also won't work correctly, try a high-resistance (~1MΩ) feedback from output to sig_out.

 

[shaikss]

Right. But you can see that the inversion from mm_out to sig_out isn't working correctly.

Above I already suspected (2) that this stage (now: M7-M3,M10) isn't configured correctly, because M10 is off and cannot lead current. Try and change the connection from its gate to its drain (instead of to its source) - or even totally remove M10 (or bridge from M3's source to gnd - just for a trial).

If the latch function also won't work correctly, try a high-resistance (~1MΩ) feedback from output to sig_out.

Yes, the inversion from mm_out to sig_out is not working. I already tried by connecting gate to drain. Then, again it behaves like a inverter. I completely see an inverted input signal at the output. If M3 source is grounded, then again its a inverter.

I will try out your last suggestion.
[QUOTE
I will try out your last suggestion.[/QUOTE]

Connecting a high resistance doesn't help.
What should be the work around in order to make it work?

 

[erikl]

Connecting a high resistance doesn't help.
What should be the work around in order to make it work?

Pls. show your schematic as it is now, and the new simulation results like those in your posting above! Perhaps then we can help you.