ASIC Verification Tools (V-Model)

[Dark_Alfred]

Hi,
I have a question about the ASIC Design-Flow and the Tools that are used.
I just watched youtube "FPGA vs ASIC Design Flow" from Xilinx and in That video, he has a Slide which shows the ASIC Design Flow.
My question is:
What Tools are used to do:
- Post-Synthesis Static Timing analysis
- Post-Synthesis Equivalency Checking
- Post Place and Route Static Timing analysis (same tools as for the first Timing analysis ?)
- Post Place and Route Timing Simulation
- Post Place and Route Verification of (Deep Sub-Micron) 2nd and 3rd order effect
?

Thanks for your answers

 

[tariq786]

please post a link to the video that you are referring to

Now to your questions

post-synthesis STA = synopsys primetime tool
post-synthesis EC = synopsys formality or cadence conformal EC
post P&R STA = synopsys primetime tool
post P&R timing simulation=synopsys VCS or Cadence NCVerilog simulator
post P&R verification of 2nd and 3rd order effects= NOT SURE

 

[Dark_Alfred]

please post a link to the video that you are referring to

FPGA vs ASIC Design Flow

Thanks for your quick answer