ASIC synthesis Vs FPGA synthesis

[anjali]

i'm using synplifyPro for FPGA synthesis & dc for ASIC synthesis.

synplifyPro uses wired AND logic and dc uses wired OR logic, i feel.

still any more differences in synthesis process among them?

 

[rakeshnunna]

We need to take care of gated clocks differently,since gated clocks cant be implemented in a FPGA

 

[anjali]

in asic synthesis, we can synthesize module alone by constaraining the remaining modules as "dont touch". then that block alone will be synthesized & with the optimized boudaries of that module.

like that can we do in FPGA synthesis using synplifyPro.

Added after 53 seconds:


in asic synthesis, we can synthesize module alone by constaraining the remaining modules as "dont touch". then that block alone will be synthesized & with the optimized boudaries of that module.

like that can we do in FPGA synthesis using synplifyPro.

 

[eeeraghu]

I don't have an idea of synplify tool, But the above said differences is thedifference between twoo tools stength to synthesis and not the differences of ASIC and FPGA synthesis. quiet well there are lot of differences while synthesizing, i.e is for while instantiaing RAM's in FPGA's(in built), using the appropriate no of available resources available in FPGA's. etc

regards
Raghu

 

[stocking]

I had been used both tools, but I deem DC is better tool for synthsis for asic or FPGA. of course, synplify pro is also used on PC computer!

 

[beckchm]

DC is the best tool for synthesis

FPGA uses the fixed cells to implement the design

ASIC uses different std cells to map the design

 

[andromeda]

There are more diferences the similarities between ASIC and FPGA synthesis:
- target libraries have no similarities at all
- scan insertion has no sence in FPGA world; memory BIST has no sence to; any DFT has no sence because FPGA are premanufactured and tested already
- clock tree synthesis is predone in FPGA; same for PLLs
- you don't need wire-load models in FPGA
- clock gating have almost no importance in FPGA. Still, if you are doing FPGA prototyping and want to check this feature on FPGA, gated clock conversion is supported by Synplify Proto and Certify (not sure about Synplify Pro).
- all Synplicity tools have top-down synthesis aprouch (for example, if you use Certify and design occupies sevaral FPGAs, synthesis is still top-down). DC still works best with bottom-up. If you are using Cadence RC for ASIC synthesis, top-down aprouch is the best again.
- insead of using Memory Compiler hard-macroes for memories, in FPGA flow on-chip dual-port memories are simple members of FPGA target library
- sythesis scripts are much more simple for FPGA synthesis (for example you don't need to put false paths through memory test-collars)
- in FPGA, you don't need and have tools like Module Compiler
- both current FPGA and ASIC sythesis tools still have problem with some Verilog2001 support, mainly with pointers. Each new tool version synthesise pointers better then previous one, but still results are very different between tools and somethimes extremely bad.

 

[newbiebk]

any of you tell me about different between FPGA and ASIC?

 

[kumar_eee]

When we wll go for DFT?...

 

[anjali]

before P&R