ASIC flow for power estimation

[inputoutput]

Presently I'm following the power optimization flow described in the Power Compiler (Version D-2010.03-SP2) described on page 2-3. Essentially the flow is:

- Simulate RTL and generate SAIF
- Synthesize in DC compiler to get gate-level netlist
- Place and route design
- Simulate gate-level or placed netlist to generate new SAIF
- Re-synthesize in DC/Power compiler to perform power optimization and get power consumption of design

My question is if a placed netlist is used for the power optimization (last step), does the place and route step need to be performed again? Is it typical to route a design twice or more? I imagine for very large designs this might not be viable?

 

[slutarius]

Hi,

Once you change the netlist for whatever reason, it should be a bunch of things to do afterward.
- Formal verification
- DFT insertion
- CTS, Place & Route.

In case of your flow, there MUST have some guidance for p&n steps from the last step.
So that, the final design would have better power consumption.

 

[ThisIsNotSam]

Presently I'm following the power optimization flow described in the Power Compiler (Version D-2010.03-SP2) described on page 2-3. Essentially the flow is:

- Simulate RTL and generate SAIF
- Synthesize in DC compiler to get gate-level netlist
- Place and route design
- Simulate gate-level or placed netlist to generate new SAIF
- Re-synthesize in DC/Power compiler to perform power optimization and get power consumption of design

My question is if a placed netlist is used for the power optimization (last step), does the place and route step need to be performed again? Is it typical to route a design twice or more? I imagine for very large designs this might not be viable?

This is one flow, it is not the only flow. Here is my view on the problem:

- Simulate RTL and generate SAIF/VCD
- Synthesize in DC compiler to get gate-level netlist of a block
- Place and route the block design
- Simulate gate-level placed netlist to generate new SAIF/VCD
- Use SAIF/VCD as input for the backend P&R tools
- Measure power with the backend tool. This is as accurate as you can get.
If power budget violated, trigger resynthesis with new targets, start over.

 

[inputoutput]

Thanks for your suggestions @Sam and @slutarius