ASIC design costas bpsk demodulator

[vishal.takodara]

I want to know about how to construct a 43 tap FIR filter in verilog using "Generate" function in verilog, if you could please guide me, I am trying to make "costas loop " for demodulation and extraction of 8bit data word from 10 bit encoded BPSK transmission at 2 MHz, the system will work at CLK - 200MHz.

I am trying to get all the modules in line, NCO, 43 tap FIR-filter, Multipliers, sin - cos tables.. everything...I would be grateful if you can help me get the idea any way possible..