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ASIC CMOS opamp design

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Junior Member level 2
Jun 8, 2009
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Hi guyz,

The following is my design problem.

Need to design a CMOS opamp in the TSMC 0.35um process. Supply voltage is 3.3V

Some of the design considerations are as follows:
1. The opamp will be set-up in the non-inverting configuration.
2. high open loop gain >80dB
3. high unity gain bandwidth requirement > 300MHz
4. needs to have a sufficient closed loop gain
5. output voltage level needs to be at 0V.

Have started the design assuming a 2-pole amplifier. Thinking of a design with 2 stage with miller cap and nulling resistor. This provides high gain but not sufficient bandwidth. What techniques can be used in this config?

Any inputs is greatly appreciated!

You don't mention few important requirements - for example what is the output swing, what is the phase margin you're shooting for, what is the input common mode range since you're considering non-inverting configuration. If you want 300MHz of unity gain frequency and a PM=60-70deg, you'll need to make the non-dominant pole 2-3x higher, that is 600-900MHz. Given you're using 0.35u technology with an Ft of probably around 10GHz, you'll have hard time to push the non-dominant pole close to 1/10 of Ft. Will burn a lot of current to boost the gm of the second stage. This is just a limitation from the technology. This said, have you considered using a gain-boosted cascode OTA? But then the output swing can be problematic and may be the input common-mode range.


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If it is a buffer job, you may want to consider a
current feedback amplifier style. It's easier to make
stable high bandwidth. Not sure I've seen one with
an output that swings to ground (and any time you
swing to the rail, your gain is liable to go in the toilet
unless maybe you have a resistor loaded source
follower output, which is not the norm for low power

Is there a reason why an amplifier cascade cannot
be used? 2 wideband amps of modest gain may be
easier to realize. Do you -have- to make it a single
canonical-appearing "op amp", or is this just your
starting concept?


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The output voltage swing needs to be 2 v peak to peak as this voltage is to be input to a pipeline ADC. I did think of implementing a cascode output stage to boost the output resistance to obtain a high gain! i could manage to obtain a unity gain bandwidth of around 200MHz but gain achieved was around 60dB.
Does look like i need to implement gain boosting techinques.

Please disregard the output at 0v specification!

I haven't thought of the possibility of implementing as a cascade. Maybe i need to explore more on how current feedback amplifiers work.
Anyways thanks a lot for your responses

Added after 2 minutes:

Another quick question.

How do i work with a design where i have a specification for achieving a closed loop gain and frquency of say 50Mhz corresponding to a gain of 20dB (just an example!)

I believe you need to use gain boosting to get your gain up to 80dB but it might create a pole-zero doublet right around your unity-gain frequency. I designed a similar buffer with a gain-boosted folded-cascode op-amp. The gain was 82dB and the unity-gain frequency was 360MHz. The technology was 0.15um though...


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Yes, JoannesPaulus is right. Now we know that you need this amplifer for an ADC which means that you'll need to settle fast within a certain time. If you design a gain boosted amplifier you need to take good care about the doublet, otherwise you won't be able to settle within the required accuracy for the time you have. Search for the paper by Klaas Bult on that issue. May be it can help in your case.


What i meant to say was the output from the op-amp which i want to design will be an input to the pipeline ADC. the op-amps to be used in the ADC will not be designed by me!

Thanks a lot for your inputs! Will try the design for gain boosting and folded cascode configs.

@JoannesPaulus : Could you guide me for the design you arrived at?. Did you use any standard configuration?

Thanks again!

It was a very standard gain-boosted fully-differential folded-cascode amplifier. The gain boosting amplifier was a simple single-ended source follower (4 of them).
It also was 7 years ago...

Another requirement in my design is a single ended output. Please correct me if i am wrong, but this requires a mirroring of current to the output which creates a pole (am i right??!!).
More than gain i require a very high bandwidth in my design. After some other considerations the following could be my final specs
open loop gain >60dB
unity gain frequency : 800MHz to 1 GHz
output swing: 2V

The amplifier will definitely be used in a non-inverting configuration: Here's the catch though:
The negative terminal will be connected to an antenna (which acts like a capacitor) and excitation to the antenna will be from the positive terminal.
The circuit starts behaving like a differentiator. (basically there a zero occurs before a pole)Can anyone help me please!

How do i go about designing such a amplifier!
any inputs will be of great help!

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