Array initialization in SystemVerilog

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chandan_c9

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Hi All,

Why is it not possible to initialize array like reg [7:0] mem [0:3] = '{'h0,'h1,2{'h0}};
:smile:
 

Because that's no legal syntax.

Just do:

reg [7:0] mem [0:3] = '{'h0,'h1,'h0,'h0};
 
I think this is because the 2{'h0} can be assigned to something like reg [0:3][7:0] mem only.
If you put [0:3] after mem, you must assign them separately.
 
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