Array assignements in verilog

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sujithchakra

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verilog array slice

Could any one please help me..... whats wrong in the following statements?

reg [7:0] a [0:7];

a[1][0]<=1'b1; // I GET "SYNTAX ERROR" here when I try to assign "1" to

element indexed [1][0] .I am using Cadence Verilog - XL to compile the code.

I find the syntax right.Could anyone please correct me if I am wrong?


Thank you
 


Verilog doesn't allow array/mem slicing beyond 1-D. Try:

Code: 
reg [7:0]  a [0:7];
reg [7:0] a_temp;


a_temp = a[1];       
a_temp[0] = 1'b1;
a[1] = a_temp;

Basically slice it into an intermediate variable and slice it as you like.

BTW - if you move to SystemVerilog, this is allowed as per your original code, but Verilog-XL won't support it, move to NC.

Cheers
Ajeetha, CVC
www.noveldv.com
 
Hi....

I think u have declare a one-dimensional array and assigning to two dimensional array that's why it's giving an syntax error.

What u hv declare is 1-D array of width 8bit.....
For 2-D array: it is
reg [7:0] arr [7:0][7:0];[/code]
 

verma.ind,
I am afraid you've got it wrong my friend. The original code(sujithchakra) was correct but as Aji explained it is not possible in verilog to do this kind of assingment , systemverilog however does allow you to write this.

If you have absoultely got to do this then try this.

reg [7:0] a [0:7];
a[1] = a[1] | 8'b1 ;

This would work fine (For simulation only)
 


That is not correct. Verilog-2001 allows 2-D unpacked array slicing (at least on the right-hand side of an assignment-operation), I use it all the time. But Verilog-XL is not Verilog-2001 compliant, so it will not recognize Verilog-2001 syntax.
 

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