arm946es synthesis script--sharing with you!

verilog tcl replace constant scripts

#----------------------------------------------------------------------------

# Set option values

set verbose 1 ;# 1 for verbose source and change_names commands

set rtl_language verilog ;# verilog or vhdl source RTL

set rundc 1 ;# 1 to start from RTL, 0 for existing db
set rtl2pg 0 ;# 1 for rtl to placed gates flow, 0 for rtl to gates

set use_clock_gating 0 ;# use RTL clock gating with Power Compiler
set integrated_cell 0 ;# tells Power Compiler to use integrated CG cell

set scan_ready 1 ;# A test ready compile will be performed
set scan_insertion 1 ;# Will cause the scan chains to be stitched
set numscanchains 4 ;# The number of scan chains to be implemented

set ultra 0 ;# Enable DC-Ultra (requires license)
set use_physopt 0 ;# Enable PhysOpt commands
set use_boundary_opt 0 ;# Enable boundary optimization
set force_wireload 0 ;# Use a custom Wire-load model
set flatten 0 ;# Remove all hierarchy from the design

set clk_period 5.5 ;# Target clock period in ns
set io_clk_period 5.5 ;# Target I/O clock period in ns
set clk_uncertainty 0.20 ;# Expected clock skew in ns
set min_latency 0 ;# Minimum clock latency under WCS
set max_latency 0 ;# Maximum clock latency under WCS

set apply_name_rules 1 ;# Change the names according the verilog names rule
set perled 0 ;# Applies the PERLED_MUX constant when parsing RTL

# ---------------------------

# Read in the technology specific scripts
if { $verbose } {
source -echo -verbose ./scripts/tsmc18.tcl
source -echo -verbose ./scripts/dont_use.tcl
} else {
source -echo ./scripts/tsmc18.tcl
source -echo ./scripts/dont_use.tcl
}

# Define the design library
define_design_lib work -path ./lib

if { $ultra } {
set_ultra_optimization true -force
}

if { $rundc } {
# Analyze the source RTL

set verilog_files { A946ESConstants.v A946ESParams.v \
a9esClkBlk.v a9esWRegDecoder.v a9esREG.v a9esFwd.v a9esRegC.v a9esIMM.v\
a9esIPipe.v a9esISyncr.v a9esMASeq.v a9esMainSeq.v a9esMem.v a9esPSR.v \
a9esPipeCtl.v a9esRegFwd.v a9esShALUADec.v a9esShALUTDec.v \
a9esShALUSeq.v a9esShALUCtl.v a9esWRegDec.v a9esMulCtl.v a9esCoreCtl.v \
a9esLU.v a9esSat.v a9esAU.v a9esArmShifter.v a9esShifter.v \
a9esSatTimes2.v a9esCLZ.v a9esExecute.v a9esRam3r2wSDff.v a9esByteRot.v\
a9esDAOut.v a9esIAOut.v a9esRegBank.v a9esMulDP.v a9esCoreDP.v \
a9esWptctl.v a9esDbgCommsctl.v a9esICEctl.v a9esTapScanctl.v \
a9esDbgctl.v a9esWptdp.v a9esDbgCommsdp.v a9esICEdp.v a9esTapScandp.v \
a9esDbgdp.v a9esDbg.v ARM9ES.v A946ESRegFile16x40.v A946ESFifo.v \
A946ESAHBBiuWb.v A946ESCPIntf.v A946ESCaRepl.v A946ESProtUnit.v \
A946ESClkGate.v A946ESETMBuf.v A946ESHitDet.v A946ESDaCntrl.v \
A946ESInsCntrl.v A946ESIntClken.v A946ESLdmStmTrk.v A946ESCp15.v \
A946ESCaTCMCntrl.v A946ESCore.v A946ESDValidMux.v A946ESIValidMux.v \
A946ESDValid.v A946ESIValid.v A946ESRBistShell.v A946ESDCache.v \
A946ESDTag.v A946ESDDirty.v A946ESICache.v A946ESITag.v A946ESRBistCtl.v \
ARM946ES.v }

set vhdl_files { a9esComponents.vhd a9esConstants.vhd a9esSat.vhd \
a9esArmShifter.vhd a9esDbgCommsctl.vhd a9esWptctl.vhd \
a9esDbgCommsdp.vhd a9esWptdp.vhd a9esISyncr.vhd a9esFwd.vhd \
a9esREG.vhd a9esRegC.vhd a9esShALUTDec.vhd a9esShALUSeq.vhd \
a9esShALUADec.vhd a9esWRegDecoder.vhd a9esAU.vhd a9esCLZ.vhd \
a9esLU.vhd a9esSatTimes2.vhd a9esShifter.vhd a9esRam3r2wSDff.vhd \
a9esICEctl.vhd a9esTapScanctl.vhd a9esICEdp.vhd a9esTapScandp.vhd \
a9esIMM.vhd a9esIPipe.vhd a9esMASeq.vhd a9esMainSeq.vhd \
a9esMem.vhd a9esMulCtl.vhd a9esPSR.vhd a9esPipeCtl.vhd \
a9esRegFwd.vhd a9esShALUCtl.vhd a9esWRegDec.vhd a9esByteRot.vhd \
a9esDAOut.vhd a9esExecute.vhd a9esIAOut.vhd a9esMulDP.vhd \
a9esRegBank.vhd a9esDbgctl.vhd a9esDbgdp.vhd a9esDbg.vhd \
a9esCoreDP.vhd a9esCoreCtl.vhd a9esClkBlk.vhd ARM9ES.vhd \
A946ESParams.vhd A946ESConstants.vhd A946ESFunctions.vhd \
A946ESComponents.vhd A946ESFifo.vhd A946ESAHBBiuWb.vhd \
A946ESHitDet.vhd A946ESCaRepl.vhd A946ESProtUnit.vhd \
A946ESDaCntrl.vhd A946ESInsCntrl.vhd A946ESIntClken.vhd \
A946ESLdmStmTrk.vhd A946ESCp15.vhd A946ESCaTCMCntrl.vhd \
A946ESCPIntf.vhd A946ESETMBuf.vhd A946ESClkGate.vhd \
A946ESCore.vhd A946ESRAMComponents.vhd A946ESICache.vhd \
A946ESITag.vhd A946ESDCache.vhd \
A946ESDTag.vhd A946ESDDirty.vhd A946ESDValidMux.vhd \
A946ESIValidMux.vhd A946ESDValid.vhd A946ESIValid.vhd \
A946ESRBistShell.vhd A946ESRBistCtl.vhd ARM946ES.vhd }

if { $rtl_language == "verilog" } {
if { $perled } {
analyze -f verilog -define PERLED_MUX $verilog_files
} else {
analyze -f verilog $verilog_files
}
} else {
if { $perled } {
analyze -f vhdl -define PERLED_MUX $vhdl_files
} else {
analyze -f vhdl $vhdl_files
}
}

if { $use_clock_gating } {
if { $scan_ready } {
if { $integrated_cell } {
set_clock_gating_style -sequential_cell latch \
-positive_edge_logic {integrated:TLATNTSCAX8} \
-control_point before -control_signal scan_enable \
-max_fanout 8
} else {
set_clock_gating_style -sequential_cell latch \
-control_point before -control_signal scan_enable \
-max_fanout 8
}
} else {
set_clock_gating_style -sequential_cell latch -setup 0 -hold 0
}
elaborate -update -gate_clock ARM946ES
} else {
elaborate -update ARM946ES
}

# Uniquify and link the design
current_design ARM946ES
uniquify
link

# Identify the scan style and hookup the testports of all clock gating elements
if { $scan_ready } {
set_scan_configuration -methodology full_scan -style multiplexed_flip_flop
set_scan_signal test_scan_enable -port SCANEN
create_net SCANEN
connect_net SCANEN [find port SCANEN]
if { $use_clock_gating } {
hookup_testports
}
}

redirect ./report/ARM946ES.check_design {check_design}

create_clock -period $clk_period CLK
set_clock_uncertainty -setup $clk_uncertainty CLK
set_clock_uncertainty -hold $clk_uncertainty CLK
set_clock_transition 0 CLK

create_clock -period $clk_period UnGatedCLK
set_clock_uncertainty -setup $clk_uncertainty UnGatedCLK
set_clock_uncertainty -hold $clk_uncertainty UnGatedCLK
set_clock_transition 0 UnGatedCLK

# Identify the high fanout nets and set the context for the design
set high_fanout [list CLK UnGatedCLK SCANEN HRESETn DBGnTRST DBGTCKEN]
set_ideal_net $high_fanout

set_load $load_value [list [all_outputs]]
set_driving_cell -cell $driving_cell_name -pin $driving_cell_pin [\
list [remove_from_collection [all_inputs] $high_fanout]]

# Set the IO timing
if { $verbose } {
source -echo -verbose scripts/arm946es_constraints.tcl
} else {
source -echo scripts/arm946es_constraints.tcl
}

# Identify wire load model and operating conditions
if { $force_wireload } {
set_wire_load_model -name $wireload_model -library $wireload_library
set_wire_load_mode top
} else {
set auto_wire_load_selection true
set_wire_load_mode top
}

# Set the operating conditions
set_operating_conditions slow

# Set specific compile options
set_max_area 0
set_max_transition 1 ARM946ES
set_resource_implementation use_fastest
foreach_in_collection design [get_designs "*"] {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
echo " ** Setting set_fix_multiple_port_nets -all -buffer_constants ** "
}
current_design ARM946ES
set_critical_range 0.2 ARM946ES

# Propagate constraints if using clock gating
if { $use_clock_gating } {
propagate_constraints -gate_clock
}

# Create test ports for scan in and scan out
current_design ARM946ES
if { $scan_insertion } {
for { set i 1 } {$i <= $numscanchains} {incr i} {
set port_name [ format "%s%s" SCANIN $i ]
create_port $port_name -direction in
set_scan_signal test_scan_in -port $port_name
}
for { set i 1 } {$i <= $numscanchains} {incr i} {
set port_name [ format "%s%s" SCANOUT $i ]
create_port $port_name -direction out
set_scan_signal test_scan_out -port $port_name
}
}

# Compile the ARM946E-S top down
current_design ARM946ES

redirect ./report/ARM946ES.check_timing {check_timing}

if { $flatten } {
ungroup -all -flatten
}

if { $rtl2pg } {
read_pdef ./floorplan/ARM946ES.pdef
if { $scan_ready } {
compile_physical -scan
} else {
compile_physical
}
} else {
if { $scan_ready } {
if { $use_boundary_opt } {
compile -boundary_optimization -map_effort medium -scan -area_effort none
} else {
compile -scan -map_effort medium -area_effort none
}
} else {
if { $use_boundary_opt } {
compile -boundary_optimization -map_effort medium -area_effort none
} else {
compile -map_effort medium -area_effort none
}
}
}

} else {

# Read existing DB
read_db ./db/ARM946ES-existing.db
current_design ARM946ES
link
}

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
read_pdef ./floorplan/ARM946ES.pdef
set physopt_pnet_partial_blockage_layer_names {METAL1 METAL2}
physopt -timing_driven_congestion -area_recovery
#Remove PhysOpt license
remove_license PhysOpt
}

# Insert scan into the design
if { $scan_insertion } {

set_test_hold 1 TESTMODE
set_scan_configuration -methodology full_scan -style multiplexed_flip_flop\
-chain_count $numscanchains -dedicated_scan_ports true -add_lockup true\
-clock_mixing mix_clocks_not_edges -replace false

set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 90
set test_default_period 100

set test_stil_multiclock_capture_procedures true

set test_stil_netlist_format verilog

create_test_clock [list UnGatedCLK CLK ] -period 100 -waveform {45 55}

# reapply set_fix_multiple_port_nets
foreach_in_collection design [get_designs "*"] {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
echo " ** Setting set_fix_multiple_port_nets -all -buffer_constants ** "
}
current_design ARM946ES

redirect ./report/ARM946ES-preinsert.dft { check_dft }

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
insert_dft -physical -map_effort high
physopt -eco -incr
#Remove PhysOpt license
remove_license PhysOpt
} else {
insert_dft -map_effort high
#perform incremental compile to remove assign statements
compile -incremental_mapping -map_effort low -area_effort none
}


redirect ./report/ARM946ES-physical.dft { check_dft }
redirect ./report/ARM946ES.scanpath { report_test -scan_path }
}

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
check_legality
#Remove PhysOpt license
remove_license PhysOpt
}

if { $apply_name_rules } {
if { $verbose } {
change_names -rules verilog -hierarchy -verbose > ./report/ARM946ES.change-names
} else {
change_names -rules verilog -hierarchy > ./report/ARM946ES.change-names
}
}

# Save the design
write -f db -hierarchy -o ./db/ARM946ES.db
write -f verilog -hierarchy -o ./db/ARM946ES.v
write_sdc -version 1.2 ./db/ARM946ES.sdc

# Report on the design

# Generate an area report for each module
redirect ./report/ARM946ES.area { echo "" }
foreach_in_collection design [get_designs "*"] {
current_design $design
redirect -append ./report/ARM946ES.area { report_area }
}
current_design ARM946ES

# Generate general reports
redirect ./report/ARM946ES.hier { report_hierarchy }
redirect ./report/ARM946ES.qor { report_qor }
redirect ./report/ARM946ES.path-group { report_path_group }
redirect ./report/ARM946ES.detail { report_design }
redirect -append ./report/ARM946ES.detail { report_clock -attributes -skew }
redirect ./report/ARM946ES.port { report_port -verbose }

# Generate fanout reports for the high fanout nets
redirect ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from CLK }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from UnGatedCLK }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from HRESETn }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from DBGnTRST }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from DBGTCKEN }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from SCANEN }

# Look for latches and combinational loops
redirect ./report/ARM946ES.latches { all_registers -level_sensitive }
redirect ./report/ARM946ES.loops { report_timing -loops }

# Generate timing reports
redirect ./report/ARM946ES.input-max-timing { report_timing -delay max -max_paths 500 -from [all_inputs]}
redirect ./report/ARM946ES.output-max-timing { report_timing -delay max -max_paths 500 -to [all_outputs]}
redirect ./report/ARM946ES.reg2reg-max-timing { report_timing -delay max -max_paths 500 -from [ all_registers -clock_pins ] -to [ all_registers -data_pins ] }
redirect ./report/ARM946ES.vio { report_constraint -all_violators }

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
redirect ./report/ARM946ES.congestion { report_congestion -congestion_effort medium }
#Remove PhysOpt license
remove_license PhysOpt
}

if {$use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
set pdefin_use_nameprefix false
write_pdef -v3.0 -output ./db/ARM946ES.pdef
#Remove PhysOpt license
remove_license PhysOpt
}

quit

high_fanout

I am still new to physical synthesis and would like to ask a question. The file ARM946ES.pdef is generated automatically?

Can you please, if possible, give an example of a pdef file.

Thanks

set_scan_signal site:edaboard.com

In your script, you illustrate how to synthesis ARM946, but I want to know why not use hard core or netlist .In this method ,the only thing you do is to merge the layout. Can you tell me the reason?

get_license power compiler

thanks!
recently, I study PKS, could you provide with PKS scripts in this flow~~~