dpaul
Advanced Member level 5
I am using Modelsim for simulation.
In my top_tb I have used VHDL alias.
When I simulate my design, I do not find the name of that alias in the Modelsim 'Objects' pane. Is this inherently how Modelsim works?
Or is there a way of enabling what I want to display at the Modelsim 'Objects' pane?
Well I have a workaround for this problem. I am just curious if Modelsim works this way with VHDL alias or there is way to get the alias displayed (I just want to add this to the Wave window).
In my top_tb I have used VHDL alias.
When I simulate my design, I do not find the name of that alias in the Modelsim 'Objects' pane. Is this inherently how Modelsim works?
Or is there a way of enabling what I want to display at the Modelsim 'Objects' pane?
Well I have a workaround for this problem. I am just curious if Modelsim works this way with VHDL alias or there is way to get the alias displayed (I just want to add this to the Wave window).