Are VHDL alias names not visible at the Modelsim 'Objects' pane?

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dpaul

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I am using Modelsim for simulation.
In my top_tb I have used VHDL alias.

When I simulate my design, I do not find the name of that alias in the Modelsim 'Objects' pane. Is this inherently how Modelsim works?
Or is there a way of enabling what I want to display at the Modelsim 'Objects' pane?

Well I have a workaround for this problem. I am just curious if Modelsim works this way with VHDL alias or there is way to get the alias displayed (I just want to add this to the Wave window).
 

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I am not a Modelsim's expert, but perhaps your aliases are not unique or in the script you somewhere closes and re-opens dataset?
If later, you need to remap aliases into opened dataset. as described in the Modelsim's Reference Manual:
 

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As far as I have understood this has nothing to do with the display of "VHDL2008 alias" at the ModelSim Objects window (so that it can be added to the Wave window).
What you have posted is some Modelsim alias for a Modelsim dataset.

My workaround for what I want to do works fine so I am keeping that. The VHDL alias (of type signal) just needs to be assigned to a locally defined signal which can then be added to the Wave window. I was looking for a way to avoid the declaration of this local signal.
 

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Well it is easy...
Code: 
    .
    .
    stim_start_p: process
        alias ddr3_ready is <<signal device_pf_top.amba_block.ddr3_ready_o : std_logic>>;
        
    begin
        ddr3_mem_rdy <= ddr3_ready; -- Transitions of the alias "ddr3_ready" can be tracked using this signal
        .
        .
 

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I notice you've put the alias in a process. Where were you looking for the alias object to add to the wave window? its been a while since I used modelsim (4 years) but IIRC variables local to a process were listed in the "locals" window when the process was selected. I expect thats where you would find aliases also?
 

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