Are there some tools help one to write testbench(vhdl)?

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ddt694

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Are there some tools help one to write testbench (vhdl)?

in a complex design, write testbench is a very troubling thing.
 

Hi Guy,

**broken link removed**
**broken link removed**

Try to use google for more.

SphinX
 

vera or e is your select! you can get some good information from : verificatoin.com
 

And one more interesting tool for generating testbenches from timing diagrams:
www.timingtool.com
 

One more comes from h**p://www.hightech-td.com/
Looks pretty nice and works for both VHDL and Verilog. Supports formulas. Shareware.

Ace-X.
 

Xilinx System Generator for simulink can generate vhdl test benches.
 

A good test bench need to emulate CPU interface, all the interface emulation/driver/monitor. That's pretty complicated.
 

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