entity FourBitAdder is
Port(X,Y: in std_logic_vector(3 downto 0);
[B]Ci: in std_logic;[/B]
S: out std_logic_vector(3 downto 0);
[B]Co: out std_logic);[/B]
end FourBitAdder;
architecture Behavorial of FourBitAdder is
signal c : std_logic_vector (2 downto 0):="000";
component FullAdder
Port(A,B,Cin: in std_logic;
R, Cout: out std_logic);
end component;
begin
bit1: FullAdder port map (A=>X(0), B=>Y(0), R=>S(0), [B]Cin=>Ci[/B], Cout=>c(0));
bit2: FullAdder port map (A=>X(1), B=>Y(1), R=>S(1), Cin=>c(0), Cout=>c(1));
bit3: FullAdder port map (A=>X(2), B=>Y(2), R=>S(2), Cin=>c(1), Cout=>c(2));
bit4: FullAdder port map (A=>X(3), B=>Y(3), R=>S(3), Cin=>c(2), [B]Cout=>Co)[/B];
end Behavorial;