[SOLVED] Are my solutions correct?

[Ohman]

Hello, im practicing on my exam to come, and im trying an old exam, i did answer two questions but im very unsure wether they are correct or not, since it was a long time since i wrote VHDL. I would appreciate if someone could check those answers and tell me if something is wrong .

a) using VHDL, implement a component for a full adder, using A,B and Cin as inputs, R and Cout as outputs
solution:

entity FullAdder is
 Port(A,B,Cin: in std_logic;
        R,Cout: out std_logic);
end FullAdder;

architecture Behavorial of FullAdder is

begin
Cout <= (A and B) or (A and Cin) or (B and Cin);
R <= A xor B xor Cin;
end Behavorial;

b) using VHDL, implement a 4 bit adder using the full adder
solution:

entity FourBitAdder is
  Port(X,Y: in std_logic_vector(3 downto 0);
         [B]Ci: in std_logic;[/B]
         S: out std_logic_vector(3 downto 0);
         [B]Co: out std_logic);[/B]
end FourBitAdder;

architecture Behavorial of FourBitAdder is
  signal c : std_logic_vector (2 downto 0):="000";
  component FullAdder
    Port(A,B,Cin: in std_logic;
    R, Cout: out std_logic);
  end component;

begin

bit1: FullAdder port map (A=>X(0), B=>Y(0), R=>S(0), [B]Cin=>Ci[/B], Cout=>c(0));
bit2: FullAdder port map (A=>X(1), B=>Y(1), R=>S(1), Cin=>c(0), Cout=>c(1));
bit3: FullAdder port map (A=>X(2), B=>Y(2), R=>S(2), Cin=>c(1), Cout=>c(2));
bit4: FullAdder port map (A=>X(3), B=>Y(3), R=>S(3), Cin=>c(2), [B]Cout=>Co)[/B];

end Behavorial;

//ohman

 

[bhav]

where is Carryin for first stage in entity declaration?

 

[VishwanathAmbli]

declare carryin and carryout in the four bit adder entity.

 

[Ohman]

Thanks for the help!, i added carryin and carryout for the entity, but im not sure if i used them correctly in the behavorial. Changed code is in bold font!

 

[bhav]

signal c : std_logic_vector (2 downto 0):="0000";

isn't there conflict in definition

 

[Ohman]

Oh yes forgot to change that, does it look OK except for that?
thanks

 

[bhav]

yup rest look ok

just simulate it for sure

 

[VishwanathAmbli]

hello,
no need for specifying dat way, jst call it with dis command... this works fine
bit1: FullAdder port map (X(0), Y(0), S(0), Ci, c(0)); i mean no need for => signs and mentionin the var name of the component...

 

[Ohman]

Ok but then i assume i would have to change the order, dependent on the order i wrote the ports, so this would be correct:

bit1: FullAdder port map(X(0),Y(0),Ci,S(0),c(0));

am i right?

 

[bhav]

yes order must be maintained