Architecture for 10 bit DAC with 2.5v process

[liccAMS]

hello friends

we now should design of 10 bit DAC with 2.5v process.Power and noise are the most important things we need conside.INL, DNL under 1 LSB
If we use the R-2R structure,the mismatch and power may limit us to attach the requirement.
Can you give me some advices about what architecture should I use.


hoping your replay
thanks in advace

 

[Syukri]

Re: Design of 10 bit DAC

U can try current-streeering

Maybe Segmented current-steering DAC that uses Binary Thermometer Decoder

 

[liccAMS]

Design of 10 bit DAC

Maybe Segmented current-steering DAC that uses Binary Thermometer Decoder

Is there 5 LSB use thermometer code and 5 MSB use binary code,or it could be either 6+4 or 7+3.which one to take? are there any calculations for that? plz send me if there are any papers for calculations?
the speed is about 1MSPS .
thx!