arbitration

[Mtech1]

I'm reading the I2C communication protocol in link

en.m.wikipedia.org/wiki/I%C2%B2C and came across a statement about i2C Bus arbitration. I'm struggling to fully understand the concept behind this statement and would appreciate clarification.


In idle state, both the SDA (data) and SCL (clock) lines are pulled to a logic HIGH level. This is achieved by the pull-up resistors connected to these lines. When there's no active communication, these lines naturally float to the HIGH state due to the pull-up resistors.
in digital logic, when we perform an AND operation on two HIGH inputs, the result is HIGH
How do multiple master devices communicate with slave devices on the same I2C bus without conflicts, and how does the Wired-AND function facilitate this communication?

Note I don't have permission to post links that's why I haven't added full wiki links

 

[KlausST]

Hi,

Who denies permission to post links? I don't think edaboard...

I guess I2C specification is free to download. Read it.

****
Arbitration works with WIRED-AND ... plus SDA readback.
The SDA drivers are OPEN_DRAIN, and with the pull-up it automatically acts as a wired-OR.
Just compare it with the truth table of an AND.

When a master sends out data (slave address) then it reads back SDA and when it outputs a HIGH bit but reads back a LOW (sent by another master) then it immediately loses arbitration and thus should disable it's drivers.

Klaus

 

[danadakk]

Also discusses clock stretching


Regards, Dana.

 

[Mtech1]

Hi,

Who denies permission to post links? I don't think edaboard...

I guess I2C specification is free to download. Read it.

****
Arbitration works with WIRED-AND ... plus SDA readback.
The SDA drivers are OPEN_DRAIN, and with the pull-up it automatically acts as a wired-OR.
Just compare it with the truth table of an AND.


Klaus

I tried to attach a link to a wiki page for reference on the forum, but it was denied displayed message I hadn't reached the maximum number of posts.

Anyways On page 8 of the attached I2C document, it mentions that devices connected to the bus must have open-drain or open-collector outputs to perform the wired-AND function. In digital logic, when we perform an AND operation on two HIGH inputs, the result is HIGH

I understand that master send salve address and read acknowleg bit. It may be high when slave doesn't except address and low when salve except address

I don't understand how do multiple master devices communicate with slave devices on the same I2C bus without conflicts, and how does the Wired-AND function facilitate this communication?

 

[betwixt]

Either the document treats the logic as 'inverted' from the VDD point of view or it's a typo.
The I2C bus is naturally high by virtue of its pull-up resistors or current source from VDD. The logic between devices is wired-OR, any low on any device pulls all the connections on that wire low.

The communication relies on the initial state of the two wires changing to indicate a 'start' condition then the SDA line is pulled low or left to float high as the SCL line is clocked. SDA is also pulled low and left to float high, neither wire is ever driven high. The initial byte(s) sent on the SDA line are the address of the device being accessed which then normally says "I'm here" by holding the SDA line down for the next clock cycle. If data has to be transferred, it is then sent from the master or as a reply from the slave by them pulling SDA low for a zero or letting it float high for a one. It's the initial address bytes that specify which of the I2C devices is to respond, the remainder should leave their SDA lines floating (high) so they don't interfere with the selected one.

Note that the least significant bit of the address byte is reserved as the read/write selector. The I2C device will actually respond to two adjacent addresses, one when data is being sent to it and one when it is being read back.

Brian.

 

[FvM]

Another view on wired AND is to consider low bus level as dominant and high level as recessive. Any bus interface driving the line low wins. That's the essential mechanism for I2C arbitration. All details are discussed in the quoted specification.

 

[KlausST]

Hi,

M1 | M2 | SDA
 0    0    0
 0    1    0
 1    0    0
 1    1    1
This is AND and this is how wired AND on I2C works.

Klaus

 

[Mtech1]

I'm still don't understand how a single master device gains control of the I2C bus when multiple masters are trying to communicate concurrently. When two masters simultaneously attempt to send data over the I2C bus, their signals are usually combined using a logical AND operation.

This operation takes the signals from both masters as inputs and produces an output signal. In the context of logical AND, if both input signals are '1' , the output becomes '1,' . Conversely, if either or both input signals are '0,' it results in an output of '0,'

 

[FvM]

You should read chapter 3.1.7 clock synchronization and chapter 3.1.8 arbitration in UM10204 thoroughly. It describes exactly how arbitration proceeds.

A bus master is required to monitor SDA and SCL continuously and
1. Don't start a transaction if the bus is active
2. Immediately stop driving the bus if looses arbitration

 

[KlausST]

I don't understand how do multiple master devices communicate with slave devices on the same I2C bus without conflicts, and how does the Wired-AND function facilitate this communication?

I've described arbitration process in post#2.
What's exactly unclear?

Klaus

 

[Mtech1]

I've described arbitration process in post#2.
What's exactly unclear?

Klaus

I don't understand below paragraph

When a master sends out data (slave address) then it reads back SDA and when it outputs a HIGH bit but reads back a LOW (sent by another master) then it immediately loses arbitration and thus should disable it's drivers.

Klaus

I don't understand how it happens. before sending slave address any one master should generate start conditions so why you mentioned slave address. As I understand master read ack/ nak bit after sending slave address not at start of i2C communication

 

[KlausST]

Hi,

Just look at any I2C timing diagram. It's always the same:
* START condition
* 7 bit SLAVE ADDRESS
* RW bit
* ACk
....

Again: please tell exactly what's unclear. Please post a timing diagram.

Klaus

 

[betwixt]

I think the misunderstanding is because you assume each master is taking it turn to control the bus. That might be the situation but more likely the second master is intruding on the bus. Each master is basically monitoring its own output and assumes all is OK if the SDA and SCL lines do as expected. If they see either line going low unexpectedly, it means something else intruded and that starts the arbitration procedure.

Brian.

 

[Mtech1]

In a scenario where two masters want to communicate with a single slave on an I2C bus, initially, both masters can generate a Start condition simultaneously to indicate their intent to communicate. Then, both masters attempt to transmit their addresses, and they monitor the SDA line. My confusion arises when the slave acknowledges the address by setting SDA low, as both masters will read the SDA line as low. In this situation, I'm unsure how the I2C bus determines which master gains control. Could you please clarify which master will gain control of the I2C bus in this case and it happens?

 

[KlausST]

Hi,

Your thinking is when both masters are perfectly matched. Matched in frequency as well as in phase.
This is not realistic.

You always have a mismatch in frequency, thus you get a mismatch in phase.

Usually it doesn´t come to the ACK of the slave. The situation where one master sends out LOW while the other sends out HIGH-Z is very likely to happen earlier.

****
Imagine: If two of your friends try to call you on the phone ... coincidentally at the same time ...
For a human it may be "at the same time", but not for a microcontroller. It will see the difference - even if in the microseconds. And the faster one will get the ring signal.

Klaus

 

[FvM]

I2C specification is explicitly considering the case that both masters are operating synchronous because it's the worst case, no matter how likely it is.
However, if they by chance start within about a half I2C clock period, clock synchronization will keep them locked as long as they send the same bit sequence.

Once again, this situation is specifically discussed in arbitration chapter. In so far the latest question is rather ignorant respectively shows you are not reading the document you posted.

My confusion arises when the slave acknowledges the address by setting SDA low, as both masters will read the SDA line as low. In this situation, I'm unsure how the I2C bus determines which master gains control. Could you please clarify which master will gain control of the I2C bus in this case and it happens?

If both master managed to get up to this point, they surely don't loose arbitration during slave ACK. Arbitration loss can only happen after both masters send different states.