#### AkhilKalathungal

##### Newbie level 3

This requirement is for my Masters Thesis project. My professor would like to see the implementation of arbitrary precision

integer arithmetic on Altera FPGA DE-2 board. The HDL used should be

**Verilog**. One way to implement is, to modify

the NIOS ii processor architecture (which has 32 bit registers) by adding custom instructions. So, if there is a need for 1024 bit

variable support, we can have data-chunks of size 32 bits * 32 numbers to construct those 1024 bits.

(Please do not ask me to create a reg of 0:1023 or bit 0:1023 in Verilog, we would like if the synthesized core can go and fit into the hardware properly, hence need this arbitrary precision logic to be implemented somehow).

Since I am a beginner in Verilog, one question I have is there a possiblity of linked list type of implementation in Verilog?

If the above requirement was in C, we would have used a linked list structure with the first 32 bits pointing to the address of the next 32 bits, and so on. I was wondering how to implement the same in Verilog.

Please advice me here and any small hints will be really appreciated.

Thank You,

Akhil