Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

AR8327N port 0 (CPU) low throughput

Not open for further replies.


Junior Member level 3
May 23, 2016
Reaction score
Trophy points
Activity points

I am hoping that you will be able to help me with this problem.
I designed a board using the AR8327N switch IC and connected an input to Port 1 and two devices to Port 0 and Port 2.
Throughput from Port 1 and Port 2 is fine and is not a problem. The problem is with Port 0 which I didn't know that it was meant as a CPU port.
There are some registers to configure ports/flow control... so if somebody can please point me in the right direction.
Right now communication through Port 0 is working but it keeps dropping (every 2 seconds for 5seconds).

I found this in MikroTik documentation that gave me some hope.

All switch chips have a special port that is called switchX-cpu, this is the CPU port for a switch chip, it is meant to forward traffic from a switch chip to the CPU, such a port is required for management traffic and for routing features. By default the switch chip ensures that this special CPU port is not congested and sends out Pause Frames when link capacity is exceeded to make sure the port is not oversaturated, this feature is called CPU Flow Control. Without this feature packets that might be crucial for routing or management purposes might get dropped.

Since RouterOS v6.43 it is possible to disable the CPU Flow Control feature on some devices that are using one of the follow switch chips: Atheros8227, QCA8337, Atheros8327, Atheros7240 or Atheros8316.

We aren't doing any configuration to the AR8327N so the registers are in default state.

Thanks for any help.


Please post a link to the datasheets. ... it makes it easier for us to help you.
Also photos, sketches, diagrams tell more than a lot of words.

The problem is with Port 0 which I didn't know that it was meant as a CPU port.
"I didn´t know"
How can it be? The sketch on page 2 of the datasheet clearly shows it as GMII/RGMII port.

But then you say you can communicate with port0. How? you need a chip/module to translate from GMII/RGMII to a PHY port (could be wired, fiber, copper...)

And when you are not satisfied with port0 performance, why don´t you use one of the other ports? (port3...5)



Link to the datasheet for anybody else here.

I didn't know because when you look at the pinout on page 16 of the datasheet you can see that Port 0 (Channel 0) is a MDI and the MAC0 (CPU Port) and MAC6 (another RGMII port) are on different pins.

There is a MDI to PCIe bridge between the switch and the device.

I cannot use any other ports because this is embedded on the PCB and it is impossible to rework it.

This is the schematics of the switch. You can see that the two RGMII ports are on the right unless I mixed up something.
Screenshot 2022-07-28 113719.png

Also here is an application example from the datasheet that has a PC connected to the PHY0. But the weird thing here is that the MAC0 (that is Port0 I guess) is also connected to the RGMII.
Screenshot 2022-07-28 114058.png

Maybe I am missing something here.

Not open for further replies.

Part and Inventory Search

Welcome to