Hi verification guys,
As every body knows, functional verification is a difficult task, and there is no
industry standard flows/tools in the field. Most ASIC companies have their own approaches, and most of them are combinations of several the state of the art
flows/tools. Presently, we are using tranditional HDL/C testbench based flow, to
cover most direct tests, and using specman/e to cover some difficult random
tests, also using formal methods only for a thorough module level tests.
Could you guys please talk about the approach you are using for functional verification for complex systems?
Many thanks!
Regards,
rprince006,