[SOLVED] applying Set_dont_use at initial stage on clock inverters and buffers - Cadence

[kannanunni]

My timing report on initial phase shows clock buffers and inverters and this might cause considerable delay in later stages. so i want to don't use these cells after initial loading..(Cadence Encounter PVS)

but upon trying command set_dont_use [get_lib_cells Lib_name/*cLK*] true
will result in.. ERROR...

[DEV]encounter 10> set_dont_use [get_lib_cells fast.lib/*CLK*] true
**WARN: (TCLCMD-513): No matching object found for 'fast.lib/*CLK*'
**ERROR: (TCLCMD-917): Cannot find 'library cells' that match 'fast.lib/*CLK*'
**ERROR: (TCLCMD-917): Cannot find 'modules, or cells' that match ''

Can anyone help on this issue..

please provide command format and library...

Thanks in advance....

 

[artmalik]

You should see the name of the cells in the set_dont_use. I don't think the actual cell name in the libs have CLK in their name. See the usage of set_dont_use
set_dont_use [get_lib_cells scx3_cmos8rf_lpvt_tt_1p2v_25c/OA*]
OA* will work as it will disable all the cells starting with OA in their names.