Dec 18, 2008 #1 G gepo Newbie level 6 Joined Dec 9, 2008 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,438 Hi, all, I have mips.v (register level verilog code) and a tcl script of design compiler. For applying clock gating, I add such a command set_clock_gating_style -minimum_bitwidth 2 in my script. but, after the synthesis, the power report is still the same as that without that command. Do you know what is the reason or my method for applying clock gating is wrong, namely i should do more things than just adding a command? thanks a lot.
Hi, all, I have mips.v (register level verilog code) and a tcl script of design compiler. For applying clock gating, I add such a command set_clock_gating_style -minimum_bitwidth 2 in my script. but, after the synthesis, the power report is still the same as that without that command. Do you know what is the reason or my method for applying clock gating is wrong, namely i should do more things than just adding a command? thanks a lot.
Dec 19, 2008 #2 S sameer_dlh25 Advanced Member level 4 Joined Sep 21, 2005 Messages 105 Helped 15 Reputation 30 Reaction score 3 Trophy points 1,298 Location San Jose Activity points 1,882 Re: apply clock gating and then how to check whether it work Hope you must have done insert_clock_gating after that
Re: apply clock gating and then how to check whether it work Hope you must have done insert_clock_gating after that
Dec 20, 2008 #3 G gepo Newbie level 6 Joined Dec 9, 2008 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,438 Re: apply clock gating and then how to check whether it work thanks very much, it really works.