gepo
Newbie level 6
Hi, all,
I have mips.v (register level verilog code) and a tcl script of design compiler.
For applying clock gating, I add such a command
set_clock_gating_style -minimum_bitwidth 2
in my script.
but, after the synthesis, the power report is still the same as that without that command.
Do you know what is the reason or my method for applying clock gating is wrong, namely i should do more things than just adding a command?
thanks a lot.
I have mips.v (register level verilog code) and a tcl script of design compiler.
For applying clock gating, I add such a command
set_clock_gating_style -minimum_bitwidth 2
in my script.
but, after the synthesis, the power report is still the same as that without that command.
Do you know what is the reason or my method for applying clock gating is wrong, namely i should do more things than just adding a command?
thanks a lot.