clock inverters
As you know, why do we use buffers in clock tree? That's because we want to balance the skew to the CK pin of each DFF and also provide a reasonable drive strength at the CK pin of DFF.
Let's assume two inverters in the clock inverters is equal to one buffer in the clock buffers in size, power, delay etc. e.g. INVx 0.01ns delay, 0.01mW power, 0.01uA leakage, while BUFx 0.02ns delay, 0.02mW power, 0.02uA leakage. And now the latency in the clock tree is, say, 1ns. If you use the INVx, you need 100 INVx, you get 1ns delay, 1mW power consumption, and 1uA leakage. If you use BUFx, you need 50 BUFxs, you also get 1ns delay, 1mW power consumption, and 1uA leakage. more or less the same thing....?